The present invention generally relates to high performance MOS devices, and more specifically to asymmetric MOS transistors.
In digital MOS circuits, performance may be approximated by the ratio of drive current through the circuit to the load being switched by the circuit. EQU f=I/Q
In this expression, I is equal to the drive current through the transistors in the circuit, Q is the charge on the output of a circuit (the load), and f is the operating frequency of the circuit, which is a measure of performance. Thus, a digital circuit's performance can be improved by increasing its drive current and/or decreasing its load.
The drive current in a given transistor is given by the following expression: EQU I=.mu..nu.
Here, .rho. represents the linear charge density (or charge per unit length) in a MOS device channel and .nu. represents the average velocity of the charge carriers in that channel. Thus, current can be increased by increasing either the linear charge density, the charge carrier average velocity, or both along a device's drive current path.
Charge carriers in conventional MOS devices move in one of two velocity regimes demarcated by the field strength across the device channel. The first regime, known as subsaturation, is encountered at relatively low lateral field strengths, such as are commonly found in long channel devices (e.g., devices in which the effective channel length is greater than about 2 .mu.m). Here velocity increases linearly with the lateral field, e, across the channel. As the lateral field increases, so does the charge carrier velocity. At some point, however, the second velocity regime is reached: a regime referred to as "saturation." Here the increasing lateral field strength has reached or exceeded a critical field strength (ecritical) at which the velocity is no longer a linear function of field strength. Rather the carrier velocity remains constant at a "saturation velocity" (vsat) with increasing field strength. Both vsat and ecritical are material properties of the semiconductor in which conduction takes place.
Physically, at velocity saturation, the carriers have reached a fundamental limit in velocity as determined by their interactions with optical phonons of the semiconductor lattice. Thus, it may appear that performance is limited by the saturation velocity. In fact, however, a third velocity regime exists: ballistic transport. This regime exists in systems where the mean free path of the charge carriers is on the order of the distance that the carriers must travel. In single crystal silicon, the mean free path for most electrons is on the order of about 1000 .ANG. or less. At these distances, phonons do not mediate charge carrier transport. Rather, the carriers accelerate under the applied lateral field as if they were in a vacuum so that their velocity increases in proportion to the square root of the potential. Thus at relatively moderate potentials, ballistic electrons can reach velocities greatly exceeding saturation velocity.
Not surprisingly, devices in which ballistic transport plays a significant role may possess greatly improved performance. For silicon-based MOS technology, such devices would have to have an effective channel length of about 0.1 .mu.m (1000 .ANG.) or less. Unfortunately, conventional optical lithography techniques (which are employed to manufacture most MOS integrated circuits today) likely can not produce such small feature sizes without great effort.
Recently, asymmetric MOS devices fabricated by conventional optical lithographic techniques have been proposed (see the above-referenced U.S. patent application Ser. No. 08/357,436). The channel region in such devices likely can be made short enough that some electrons will move by ballistic transport. These devices include, in addition to conventional MOS device elements, a pocket region of relatively high dopant concentration abutting either the device's source or drain along the side of the source or drain that faces the device's channel region. Because the pocket region abuts only one of the source or drain, the device is deemed "asymmetric."
As explained in U.S. patent application Ser. No. 08/357,436, the pocket region locally increases the threshold voltage of the device over a very small portion of the channel region. Thus, it is believed that such asymmetric devices behave like two pseudo-MOS devices in series: a "source FET" and a "drain FET," one of which has a higher threshold voltage by virtue of the pocket region. An asymmetric MOS device having such structure will switch as follows. At a very low (typically less than -1 volt for an NFET) gate voltage, neither the shorter nor longer channel pseudo-device is switched "on." That is, neither pseudo-device's channel region has undergone inversion. However, at slightly higher gate potentials, in the range where MOS devices are normally switched off (e.g., slightly above -1 volt), the threshold of the longer channel pseudo-device is exceeded, and that device therefore has switched on. Nevertheless, such gate voltages still do not exceed the level at which the shorter channel pseudo-device switches on. Thus, no current yet flows between the source and drain. As the gate voltage increases and surpasses the shorter channel pseudo-device's threshold voltage (typically at about 0 volts), that device also switches on allowing current to flow between the source and drain. In short, the device switches on in two stages, and does not completely switch on until the gate voltage exceeds the short channel pseudo-device's threshold voltage.
If an asymmetric MOS device is operated such that the "on" gate voltage only slightly exceeds the threshold voltage of the shorter channel pseudo-device, the performance of the overall MOS device will be governed by the performance of that pseudo-device. This is very desirable if the shorter channel pseudo device has an effective channel length on the order of 1000 .ANG. or less. As noted, at such short lengths, some charge carriers move across the channel ballistically.
To realize maximum performance, the above-described asymmetric MOS device should switch at a very low gate voltage, near 0 volts. Various techniques for adjusting threshold voltage are known. For example, employing low concentrations of dopant in the channel region of a MOS device will result in a low threshold voltage. Thus for a NMOS device, lowering the p-type dopant concentration in the channel region (while fixing all other relevant variables) lowers the device's threshold voltage. Very low thresholds (on the order of 0 volts or lower) can be achieved by "counter doping" the channel region. Counter doping involves adding dopant atoms of conductivity type opposite that of the bulk dopant to the device channel region. In a NMOS device, for example, the channel region can be counter doped with n-type dopant to dramatically reduce the device threshold.
While counter doping reduces threshold voltage, and thereby theoretically improves performance in active circuits, it can also increase the resistance in the channel region. This additional resistance is due to decreased charge carrier mobility from impurity scattering in the channel region conduction path. As dopant atoms are the primary impurities causing such scattering, the effect is most pronounced in the pocket region, where both counter dopant and pocket dopant atoms reside. Unfortunately, the increased resistance can partially or completely offset any advantage provided by a lower threshold, especially in devices with low supply voltages (Vdd). As device design trends are currently moving to lower supply voltages, some technique for reducing the conduction path resistance is necessary if the potential advantages of counter doping are to be realized in asymmetric devices.